The invention relates generally to the field of semiconductors and more specifically to memory devices.
Electrically erasable programmable read only memory (EEPROM) structures are commonly used in integrated circuits for non-volatile date storage. EEPROM device structures commonly include a polysilicon floating gate formed over a tunnel dielectric, which is formed over a semiconductor substrate, to store charge. As device dimensions and power supply voltages decrease, the thickness of the tunnel dielectric cannot correspondingly decrease in order to prevent data retention failures. An EEPROM device using isolated silicon nanocrystals as a replacement to the floating gate does not have the same vulnerability to isolated defects in the tunnel dielectric and thus, permits scaling of the tunnel dielectric and the operating voltage without compromising data retention.
In order to have a significant memory effect as measured by the threshold voltage shift of the EEPROM device, it is necessary to have a high density of silicon nanocrystals of approximately 1E12 nanocrystals per cm2. One method to achieve such a density of nanocrystals is to fabricate the nanocrystals using ultra high vacuum chemical vapor deposition (UHVCVD) using disilane (Si2H6). However, the length of the process time is greater than 10 minutes per wafer, which results in undesirable increased cycle time and manufacturing costs. Other approaches to form nanocrystals on the tunnel dielectric have resulted in achieving densities significantly less than desired (e.g., 5E11 nanocrystals per cm2). Therefore, a need exists to form nanocrystals at desired densities without increasing manufacturing cycle time or cost.